Advances in chip manufacturing technology have lead to printed circuit boards with input/output drivers having very fast signal transition times. Fast signal transition times can make even short interconnects behave like transmission lines with all of the related signal integrity problems. Clock frequencies in system designs have also continued to increase. Faster clock frequencies result in tighter delay margins when designing interconnects. Thus, the challenge of today's high speed board design is to design the interconnects within the available delay margins while maintaining the desired signal quality. Signal quality is usually measured in terms of overshoot, undershoot, monotonicity, and ringback.
The above mentioned interconnect design problem is critical for high speed nets with a large number of pins. It is even more critical for nets with bi-directional drivers, since it is necessary to make sure that the timing margins and signal quality are maintained for every driver on the net.
Designing interconnects to meet the specified constraints consists of two stages. One stage is topology design and the other stage is termination selection. For example, a daisy chain topology may be designed having a series termination scheme. In today's design methodology, both stages are frequently done manually. For instance, a designer may manually explore the infinite space of possible topologies and termination schemes for each net in a design. This is a very time consuming task where the engineer has to set up simulations for each design point to verify the delay and signal quality constraints are met.
A need exists, therefore, for a design tool which can automate topology and termination selection for a general net, while adhering to delay and signal quality constraints. In particular, an automated design tool is needed for interconnecting multiple pin nets and nets with bi-directional drivers.